Dual-Metal Graded-Channel Double-Gate Tunnel FETs for Reduction of Ambipolar Conduction
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8765317/8770219/08770449.pdf?arnumber=8770449
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Final Summary and Future of Advanced Ultra Low Power Metal Oxide Semiconductor Field Effect Transistors;Advanced Ultra Low‐Power Semiconductor Devices;2023-10-27
2. Interfacial trap charge and self-heating effect based reliability analysis of a Dual-Drain Vertical Tunnel FET;Microelectronics Reliability;2023-07
3. A Review on Emerging Tunnel FET Structures for High-speed and Low-power Circuit Applications;2023 IEEE Devices for Integrated Circuit (DevIC);2023-04-07
4. Performance Investigation of a Vertical TFET with Inverted-T Channel for Improved DC and Analog/Radio-Frequency Parameters;ECS Journal of Solid State Science and Technology;2023-04-01
5. Demonstration of L-Channel Tunnel FET with Triple Metal Gate for Next Generation IC Technology;2023 3rd International conference on Artificial Intelligence and Signal Processing (AISP);2023-03-18
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