Impacts of Poly-Si Nanowire Shape on Gate-All-Around Flash Memory With Hybrid Trap Layer-Reference-Cited by-同舟云学术

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Impacts of Poly-Si Nanowire Shape on Gate-All-Around Flash Memory With Hybrid Trap Layer

Published:2011-10 Issue:10 Volume:32 Page:1382-1384
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Chen Hung-Bin,Wu Yung-Chun,Yang Chao-Kan,Chen Lun-Chun,Chiang Ji-Hong,Chang Chun-Yen

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/55/6028517/06012512.pdf?arnumber=6012512

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Applications of Nanotechnology in Next-Generation Nonvolatile Memories;Introduction to Nano;2015

2. Self-Aligned Four-Terminal Planar Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors for System-on-Glass;IEICE Transactions on Electronics;2014

3. Characteristics of gate-all-around polycrystalline silicon channel SONOS flash memory;International Journal of Nanotechnology;2014

4. Analytical Modeling of Si and Au Nanocrystal Embedded Multilayer Gate Dielectric Long Channel Gate All Around (GAA) MOSFET Non Volatile Memory Devices;Nanoscience and Nanotechnology Letters;2012-07-01

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