A 114-pW PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracy for nW systems-Reference-Cited by-同舟云学术

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A 114-pW PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracy for nW systems

Published:2016-06 Issue: Volume: Page:
ISSN:
Container-title:2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)
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Author:

Qing Dong ,Kaiyuan Yang ,Blaauw David,Sylvester Dennis

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7569797/7573453/07573494.pdf?arnumber=7573494

Cited by 16 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and Analysis of a Family of pW-Level Sub-1V CMOS VRGs by Stacking a Current-Source Transistor and a Resistive-Load Transistor;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. Performance Comparison of CMOS Based Voltage Reference Circuits in 180nm Technology;2023 9th International Conference on Signal Processing and Communication (ICSC);2023-12-21

3. A picowatt CMOS voltage reference with 0.046 %/V line sensitivity for a low-power IoT system;2023 20th International SoC Design Conference (ISOCC);2023-10-25

4. A Dual-Output Picowatt Hybrid Voltage Reference with Digital Trimming Technique;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26

5. Ultra‐low line sensitivity and high PSRR sub‐threshold CMOS voltage reference;The Journal of Engineering;2023-04

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