Ultra‐low line sensitivity and high PSRR sub‐threshold CMOS voltage reference

Abstract

AbstractThis paper presents a nanowatt CMOS voltage reference (VR) with ultra‐low line sensitivity (LS) and high‐power supply ripple rejection (PSRR). The proposed VR consists of two simple nanowatt two‐transistor (2T) VRs. Two current mirrors are associated with these VRs. The outputs of the current mirrors have different magnitudes but the same power supply dependence slope. For this purpose, the primary 2T VR has been designed with long‐channel MOSFETs, while the secondary VR utilizes medium‐channel length transistors. Low dependence on the power supply variations is achieved by subtracting these two currents, whereas the subtracted current is almost independent of the power supply. The temperature coefficient (TC) minimization is achieved separately by adjusting the transistor sizes of the primary VR. Post‐layout simulation is performed using 0.18 µm standard CMOS technology, which shows a nominal output voltage of 0.15 V, obtaining an average TC of 21.4 ppm/°C over a temperature range of 0–120°C. It achieves an excellent line sensitivity of 0.0039%/V when the supply voltage varies from 0.4 to 2 V. The dc PSRR values at 0.4 and 1 V of supply voltage are −80.1 and ‐114.2 dB, respectively at room temperature.