A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET-Reference-Cited by-同舟云学术

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A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET

Published:2018-06 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE Symposium on VLSI Circuits
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Author:

Hudner James,Carey Declan,Casey Ronan,Hearne Kay,de Abreu Farias Neto Pedro Wilson,Chlis Ilias,Erett Marc,Poon Chi Fung,Laraba Asma,Zhang Hongtao,Chaitanya Ambatipudi Sai Lalith,Mahashin David,Upadhyaya Parag,Frans Yohan,Chang Ken

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8484863/8502213/08502436.pdf?arnumber=8502436

Cited by 16 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A PAM4 transceiver design scheme with threshold adaptive and tap adaptive;EURASIP Journal on Advances in Signal Processing;2023-06-21

2. Terahertz metadevices for silicon plasmonics;Chip;2022-12

3. Design and Implementation of High Speed and Low Power 12-bit SAR ADC using 22nm FinFET;WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL;2022-01-03

4. ADC-Based SerDes Receiver for 112 Gb/s PAM4 Wireline Communication;Analog Circuits for Machine Learning, Current/Voltage/Temperature Sensors, and High-speed Communication;2022

5. ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET;IEEE Journal of Solid-State Circuits;2021-04

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