Implementation of a 4*4 10T SRAM Array using Domino Schmitt Trigger

Author:

Joy Ancy1,Joseph Megha Ann2,Kuruvilla Jinsa2

Affiliation:

1. Mar Athanasius College of Engineering, Mar Baselios College of Engineering and Technology, APJ Abdul Kalam Technological University,Kerala,India

2. Mar Athanasius College of Engineering, APJ Abdul Kalam Technological University,Department of ECE,Kerala,India

Publisher

IEEE

Reference11 articles.

1. Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells With Reverse-Biased FinFETs, Near-Threshold Operation, and Power Gating

2. Power-Gated 9T SRAM Cell for Low-Energy Operation

3. Forced-Sleep SVR SRAM for High Frequency Applications;aby;2020 International Conference on Power Electronics and Renewable Energy Applications(PEREA),0

4. Design of SRAM Cell by Using Self-Controllable Voltage Level Circuits;akshaya;International Journal of Innovative Research in Computer and Communication Engineering,0

5. A highly stable reliable SRAM cell design for low power applications

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Performance Evaluation of 9T and 6T SRAM Cells at 7nm Technology;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06

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