A Sub-Sampling PLL with Robust Operation under Supply Interference and Short Re-Locking Time
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/9043348/9056889/09056927.pdf?arnumber=9056927
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 1.5–2.56-GHz TDC-Assisted Fast-Locking Wideband Fractional-N CPPLL With Phase Noise of −138 dBc/Hz at 1-MHz Offset Frequency;IEEE Microwave and Wireless Technology Letters;2024-09
2. A 2.4-GHz Ring-VCO-Based Sub-Sampling PLL With a −70-dBc Reference Spur by Adopting a Capacitor-Multiplier-Based Sub-Sampling DLL;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-09
3. A Sub-Sampling Phase-Locked Loop with a TDC-Based Frequency-Locked Loop;2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT);2023-04-17
4. Will You Accept the AI Recommendation? Predicting Human Behavior in AI-Assisted Decision Making;Proceedings of the ACM Web Conference 2022;2022-04-25
5. A 5-GHz Sub-Sampling Phase-Locked Loop With Pulse-Width to Current Conversion;2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT);2022-04-18
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