A 1.5–2.56-GHz TDC-Assisted Fast-Locking Wideband Fractional-N CPPLL With Phase Noise of −138 dBc/Hz at 1-MHz Offset Frequency-Reference-Cited by-同舟云学术

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A 1.5–2.56-GHz TDC-Assisted Fast-Locking Wideband Fractional-N CPPLL With Phase Noise of −138 dBc/Hz at 1-MHz Offset Frequency

Published:2024-09 Issue:9 Volume:34 Page:1111-1114
ISSN:2771-9588
Container-title:IEEE Microwave and Wireless Technology Letters
language:
Short-container-title:IEEE Microw. Wireless Tech. Lett.

Author:

Xiang Ruiyong¹^ORCID,Lu Yixing¹,Luo Xiao¹,Wang Sifan¹,Zhang Bodong¹^ORCID,Shu Shengpeng¹^ORCID,Feng Haigang¹^ORCID

Affiliation:

1. Tsinghua Shenzhen International Graduate School, Tsinghua University, Shenzhen, China

Funder

Guangdong Key Area Research and Development Plan

Science, Technology and Innovation Commission of Shenzhen Municipality

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx8/9944983/10666874/10636853.pdf?arnumber=10636853

Reference11 articles.

1. A 6 to 12-GHz Fractional-N Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays

2. Design and Analysis of Sub-Sampling Phase-Locked Loop for Quantum Computing

3. A Sub-Sampling PLL with Robust Operation under Supply Interference and Short Re-Locking Time

4. Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication

5. A 0.4–6-GHz Blocker-Tolerant Receiver in 65-nm CMOS With Bandwidth-Extended Technologies for Future V2X Applications

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