Gain Cell Memory on Logic Platform – Device Guidelines for Oxide Semiconductor Transistor Materials Development-Reference-Cited by-同舟云学术

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Gain Cell Memory on Logic Platform – Device Guidelines for Oxide Semiconductor Transistor Materials Development

Published:2023-12-09 Issue: Volume: Page:
ISSN:
Container-title:2023 International Electron Devices Meeting (IEDM)
language:
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Author:

Liu Shuhan¹,Jana Koustav¹,Toprasertpong Kasidit¹,Chen Jian¹,Liang Zheng²,Jiang Qi¹,Wahid Sumaiya¹,Qin Shengjun¹,Chen Wei-Chen¹,Wong H.-S. Philip¹

Affiliation:

1. Stanford University,Department of Electrical Engineering,California,USA

2. University of California,Berkeley,California,USA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10413659/10413660/10413726.pdf?arnumber=10413726

Reference8 articles.

1. Gain-Cell Embedded DRAMs: Modeling and Design Space

2. Low-Field Electron Mobility Model for Ultrathin-Body SOI and Double-Gate MOSFETs With Extremely Small Silicon Thicknesses

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Channel Modeling for 2TOC Gain-Cell eDRAM;2024 9th International Conference on Electronic Technology and Information Science (ICETIS);2024-05-17

2. Design Guidelines for Oxide Semiconductor Gain Cell Memory on a Logic Platform;IEEE Transactions on Electron Devices;2024-05

3. Partially Isolated Dual Work Function Gate IGZO TFT With Obviously Reduced Leakage Current for 3D DRAMs;IEEE Journal of the Electron Devices Society;2024

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