Design Guidelines for Oxide Semiconductor Gain Cell Memory on a Logic Platform-Reference-Cited by-同舟云学术

Design Guidelines for Oxide Semiconductor Gain Cell Memory on a Logic Platform

Published:2024-05 Issue:5 Volume:71 Page:3329-3335
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Liu Shuhan¹^ORCID,Jana Koustav¹^ORCID,Toprasertpong Kasidit¹^ORCID,Chen Jian¹,Liang Zheng²,Jiang Qi¹,Wahid Sumaiya¹^ORCID,Qin Shengjun¹^ORCID,Chen Wei-Chen¹^ORCID,Pop Eric¹^ORCID,Wong H.-S. Philip¹^ORCID

Affiliation:

1. Department of Electrical Engineering, Stanford University, Stanford, CA, USA

2. Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, USA

Funder

Semiconductor Research Corporation (SRC) Center for Processing with Intelligent Storage and Memory

SRC Center for Heterogeneous Integration of Micro Electronic Systems

InnoHK Artificial intelligence (AI) Chip Center for Emerging Smart Systems (ACCESS) Center

Member Companies of Stanford Non-Volatile Memory Technology Research Initiative (NMTRI) and Stanford SystemX Alliance

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/16/10508280/10504765.pdf?arnumber=10504765

Reference32 articles.

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3. Capacitor-less, Long-Retention (>400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM

4. Double-Gate W-Doped Amorphous Indium Oxide Transistors for Monolithic 3D Capacitorless Gain Cell eDRAM

5. Co-designed Capacitive Coupling-Immune Sensing Scheme for Indium-Tin-Oxide (ITO) 2T Gain Cell Operating at Positive Voltage Below 2 V