An analytical model for false turn-on evaluation of GaN transistor in bridge-leg configuration
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7835398/7854636/07854840.pdf?arnumber=7854840
Cited by 15 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A 400-V Half Bridge Gate Driver for Normally-Off GaN HEMTs With Effective Dv/Dt Control and High Dv/Dt Immunity;IEEE Transactions on Industrial Electronics;2023-01
2. A Three-Level GaN Driver for High False Turn-ON Tolerance With Minimal Reverse Conduction Loss;IEEE Open Journal of Power Electronics;2023
3. A high-speed low side GaN e-HEMT driver with gate ringing and overshoot suppression;IEICE Electronics Express;2022-05-25
4. A high-speed low side GaN e-HEMT driver with gate ringing and overshoot suppression;IEICE ELECTRON EXPR;2022
5. Characterization and optimization of gate driver turn-off voltage for eGaN HEMTs in a phase-leg configuration;Energy Reports;2022-04
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