A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS-Reference-Cited by-同舟云学术

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A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS

Published:2021-09-13 Issue: Volume: Page:
ISSN:
Container-title:ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)
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Author:

Cai Chen,Zheng Xuqiang,Chen Yong,Wu Danyu,Luan Jian,Zhou Lei,Wu Jin,Liu Xinyu

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9567713/9567736/09567818.pdf?arnumber=9567818

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Fractionally-Spaced Equalizers as Clock and Data Recovery Loops;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-07

2. A 100-Gb/s PAM-8 Transmitter With 3-Tap FFE and High-Swing Hybrid Driver in 40-nm CMOS Technology;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-06

3. A high-output-swing 64-Gb/s PAM-4 transmitter with a 4-tap hybrid FFE in 28-nm CMOS;IEICE Electronics Express;2024-04-10

4. An 80-Gb/s/pin Single-Ended Voltage-Mode PAM-4 Transmitter With a Pulsewidth Pre-Emphasis and a 4-Tap FFE in 28-nm CMOS;IEEE Journal of Solid-State Circuits;2024

5. 41.6 Gb/s High-Depth Pre-Interleaver for DFE Error Propagation in 65 nm CMOS Technology;Electronics;2023-09-16

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