An 18.2μW 101.1dB DR Fully-Dynamic ΔΣ ADC with Partially-Feedback Noise-Shaping Quantizer and CLS-Embedded Two-Stage FIAs
Author:
Affiliation:
1. Zhejiang University,College of Information Science and Electrical Engineering,Hangzhou,China
Funder
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10268677/10268683/10268800.pdf?arnumber=10268800
Reference7 articles.
1. A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier
2. 27.4 A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier
3. A 600mVPP-Input-Range 94.5dB-SNDR NS-SAR-Nested DSM with 4th-Order Truncation-Error Shaping and Input-Impedance Boosting for Biosignal Acquisition
4. An Over-60 dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp With Only 30 dB Loop Gain
5. A 2.87μW 1kHz-BW 94.0dB-SNDR 2-0 MASH ADC Using FIA with Dynamic-Body-Biasing Assisted CLS Technique
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1. A Partially Feedback NSSAR Embedded Third-Order Delta–Sigma Modulator With Gain-Boosted Two-Stage FIAs;IEEE Journal of Solid-State Circuits;2024-09
2. System-Level Implementation of a Parallel-Path Hybrid Switched-Capacitor Amplifier with an Embedded Successive Approximation Register for IoT Applications;Electronics;2024-08-30
3. A sub-100 nW Power, Compact CTDSM with a Band-To-Band Tunnelling Loop Filter;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
4. A 0.5V 723nW 84.3dB-SNDR Dynamic Zoom ADC with CLS-Assisted Capacitively-Biased FIA;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
5. Inverter-based noise-shaping SAR ADC for low-power applications;Microelectronics Journal;2024-02
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