A 2.87μW 1kHz-BW 94.0dB-SNDR 2-0 MASH ADC Using FIA with Dynamic-Body-Biasing Assisted CLS Technique
Author:
Affiliation:
1. Zhejiang University,Hangzhou,China
2. Peking University,Beijing,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731544.pdf?arnumber=9731544
Reference6 articles.
1. Low-distortion delta-sigma topologies for MASH architectures
2. 27.4 A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier
3. An Over-60 dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp With Only 30 dB Loop Gain
4. A 280?W dynamic-zoom ADC with 120dB DR and 118dB SNDR in 1kHz BW;karmakar;ISSCC,2018
5. 9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier;tang;ISSCC,2020
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1. A Partially Feedback NSSAR Embedded Third-Order Delta–Sigma Modulator With Gain-Boosted Two-Stage FIAs;IEEE Journal of Solid-State Circuits;2024-09
2. An Energy-Efficient Discrete-Time Delta–Sigma Modulator With Dynamic-Range Enhancement and Tri-Level CDAC;IEEE Journal of Solid-State Circuits;2024-09
3. Analysis of Stability, Noise, and Design Guidelines for a Cascaded Floating-Inverter Amplifier;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-09
4. Low‐power multibit delta–sigma modulator based on passive and unattenuated summation scheme;International Journal of Circuit Theory and Applications;2024-06-18
5. Flip-Around Level-Shifting For Switched-Capacitor Amplifiers to Improve the Closed-Loop Settling of Floating-Inverter Amplifiers;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
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