A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training-Reference-Cited by-同舟云学术

A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training

Published:2022-09-19 Issue: Volume: Page:
ISSN:
Container-title:ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)
language:
Short-container-title:

Author:

Jeong Sangsu¹,Park Jeongwoo¹,Jeon Dongsuk¹

Affiliation:

1. Graduate School of Convergence Science and Technology, Seoul National University,Seoul,Korea

Funder

National Research Foundation of Korea

IC Design Education Center

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9911257/9911222/09911450.pdf?arnumber=9911450

Reference11 articles.

1. A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory

2. An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications;chih;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2021

3. A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration;tu;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2022

4. Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips

5. A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 19.7 TFLOPS/W Multiply-less Logarithmic Floating-Point CIM Architecture with Error-Reduced Compensated Approximate Adder;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. Energy-Efficient Brain Floating Point Convolutional Neural Network Using Memristors;IEEE Transactions on Electron Devices;2024-05

3. FP-ATM: A Flexible Floating Point NOR Adder Tree Macro for In-Memory Computing;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

4. FP-BMAC: Efficient Approximate Floating-Point Bit-Parallel MAC Processor using IMC;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

5. A Dual-Wordline 6T SRAM Computing-In-Memory Macro Featuring Full Signed Multi-Bit Computation for Lightweight Networks;IEEE Access;2024