A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization

Author:

Kneip Adrian,Lefebvre Martin,Verecken Julien,Bol David

Publisher

IEEE

Reference14 articles.

1. Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs

2. PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference

3. SRAM with In-Memory Inference and 90Activity Reduction for Always-On Sensing with 109 TOPS/mm2 and 749–1,459 TOPS/W in 28nm;rajanna;IEEE ESSCIRC,2021

4. A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing;lee;IEEE ISSCC,2021

5. STICKER-1M: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/lntra-Macro Data Reuse;yue;IEEE JSSC (Early Access),2022

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