Variation-aware layout-driven scheduling for performance yield optimization

Author:

Lucas Gregory,Chen Deming

Publisher

IEEE

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Kron-Branin modeling of symmetric star tree interconnect;International Journal of Circuit Theory and Applications;2018-10-15

2. New advances of high-level synthesis for efficient and reliable hardware design;Integration;2017-06

3. A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2017

4. A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2016

5. Joint Profit and Process Variation Aware High Level Synthesis With Speed Binning;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-09

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