A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation-Reference-Cited by-同舟云学术

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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

Published:2017 Issue:7 Volume:E100.A Page:1439-1451
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

IGAWA Koki¹,YANAGISAWA Masao¹,TOGAWA Nozomu¹

Affiliation:

1. Department of Computer Science and Communications Engineering, Waseda University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E100.A/7/E100.A_1439/_pdf

Reference23 articles.

1. [1] G. Lucas and D. Chen, “Variation-aware layout-driven scheduling for performance yield optimization,” Proc. IEEE/ACM International Conference on Computer-Aided Design, pp.17-24, 2010. 10.1109/iccad.2010.5654344

2. [2] Y. Hagio, M. Yanagisawa, and N. Togawa, “A delay-variation-aware high-level synthesis algorithm for rdr architectures,” IPSJ Trans. System LSI Design Methodology, vol.7, pp.81-90, 2014. 10.2197/ipsjtsldm.7.81

3. [3] K. Kawamura, Y. Hagio, Y. Shi, and N. Togawa, “A floorplan-aware high-level synthesis technique with delay-variation tolerance,” Proc. IEEE International Conference on Electron Devices and Solid-State Circuits, pp.122-125, 2015. 10.1109/edssc.2015.7285065

4. [4] K. Igawa, M. Yanagisawa, and N. Togawa, “A multi-scenario high-level synthesis algorithm for variation-tolerant floorplan-driven design,” IEICE Trans. Fundamentals, vol.E99-A, no.7, pp.1278-1293, July 2016. 10.1587/transfun.e99.a.1278

5. [5] J.W. Tschanz, J.T. Kao, S.G. Narendra, R. Nair, D.A. Antoniadis, A.P. Chandrakasan, and V. De, “Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage,” IEEE J. Solid-State Circuits, vol.37, no.11, pp.1396-1402, 2002. 10.1109/jssc.2002.803949

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