Author:
Mishchenko Alan,Brayton Robert,Chatterjee Satrajit
Cited by
19 articles.
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1. EffiSyn: Efficient Logic Synthesis with Dynamic Scoring and Pruning;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28
2. CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems;Proceedings of the Great Lakes Symposium on VLSI 2023;2023-06-05
3. Exploration of FPGA PLB Architecture Base on LUT and Microgates;2023 International Symposium of Electronics Design Automation (ISEDA);2023-05-08
4. Challenges of SCA-Based Verification;Formal Verification of Structurally Complex Multipliers;2022-12-20
5. Improving LUT-based optimization for ASICs;Proceedings of the 59th ACM/IEEE Design Automation Conference;2022-07-10