EffiSyn: Efficient Logic Synthesis with Dynamic Scoring and Pruning-Reference-Cited by-同舟云学术

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EffiSyn: Efficient Logic Synthesis with Dynamic Scoring and Pruning

Published:2023-10-28 Issue: Volume: Page:
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Container-title:2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)
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Author:

Li Xing¹,Chen Lei¹,Zhang Jiantang²,Wen Shuang²,Sheng Weihua²,Huang Yu²,Yuan Mingxuan¹

Affiliation:

1. Huawei Noah's Ark Lab,Hong Kong SAR,China

2. Hisilicon,Shenzhen,Hong Kong SAR,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10323590/10323543/10323902.pdf?arnumber=10323902

Reference27 articles.

1. Unlocking fine-grain parallelism for AIG rewriting

2. Batch Sequential Black-Box Optimization with Embedding Alignment Cells for Logic Synthesis

3. A Circuit-Based SAT Solver for Logic Synthesis

4. Novel-rewrite: node-level parallel aig rewriting;lin;Proc DAC 2022,0

5. HIMap

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A General Framework for Efficient Logic Synthesis;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

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