Assessment of Negative Bias Temperature Instability Due to Interface and Oxide Trapped Charges in Gate-All-Around TFET Devices
Author:
Affiliation:
1. Department of Electronics Engineering, Indian Institute of Technology, Dhanbad, Jharkhand, India
2. Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi, Jharkhand, India
Funder
Department of Science and Technology, Government of India
INSPIRE Scheme
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Science Applications
Link
http://xplorestaging.ieee.org/ielx7/7729/10016255/10065460.pdf?arnumber=10065460
Reference33 articles.
1. An analysis of interface trap charges to improve the reliability of a charge-plasma-based nanotube tunnel FET
2. A simulation-based analysis of effect of interface trap charges on dc and analog/HF performances of dielectric pocket SOI-Tunnel FET
3. Impact of Random Interface Traps and Random Dopants in High-$k$ /Metal Gate Junctionless FETs
4. Bias temperature instability in tunnel field-effect transistors
5. Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies
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