A 266.7 TOPS/W Computing-in Memory Using Single-Ended 6T 4-kb SRAM in 16-nm FinFET CMOS Process
Author:
Affiliation:
1. National Sun Yat-Sen University,Department of Electrical Engineering,Kaohsiung,Taiwan
2. Virginia Tech,Bradley Department of Electrical and Computer Engineering,Blacksburg,VA,USA
Funder
National Science and Technology Council
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10595550/10595552/10595553.pdf?arnumber=10595553
Reference14 articles.
1. A 4 + 2T SRAM for Searching and In-Memory Computing With 0.3-V $V_{\mathrm {DDmin}}$
2. X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories
3. A 4-kB 500-MHz 4-T CMOS SRAM using low-V/sub THN/ bitline drivers and high-V/sub THP/ latches
4. Multifunctional In-Memory Computation Architecture Using Single-Ended Disturb-Free 6T SRAM
5. SRAM-Based Computation in Memory Architecture to Realize Single Command of Add-Multiply Operation and Multifunction
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