Design Technology Co-Optimization for Cold CMOS Benefits in Advanced Technologies-Reference-Cited by-同舟云学术

Design Technology Co-Optimization for Cold CMOS Benefits in Advanced Technologies

Published:2021-12-11 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE International Electron Devices Meeting (IEDM)
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Author:

Chiang Hung-Li¹,Wu Jui-Jen¹,Chou Chen-Han²,Hsiao Yen-Fu²,Chen Yi-Chun²,Liu Leo¹,Wang Jer-Fu¹,Chen Tzu-Chiang¹,Liao Pei-Jun²,Cai Jin²,Bao Xinyu¹,Cheng Alan²,Chang Meng-Fan¹

Affiliation:

1. Taiwan Semiconductor Manufacturing Company,Corporate Research,Hsinchu,Taiwan

2. Taiwan Semiconductor Manufacturing Company,Hsinchu,Taiwan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9720433/9720494/09720573.pdf?arnumber=9720573

Reference18 articles.

1. Device Modeling at Cryogenic Temperatures: Effects of Incomplete Ionization

2. On the manifestation of phosphorus-vacancy complexes in epitaxial Si:P films

3. Circuit-Level Technique to Design Variation- and Noise-Aware Reliable Dynamic Logic Gates

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