Accelerating Device-Circuit Self-Heating Simulations with Dynamic Time Evolution for GAAFET
Author:
Affiliation:
1. School of Electrical and Computer Engineering, Peking University,Shenzhen,China,518055
2. School of Integrated Circuits, Peking University,Beijing,China,100871
Funder
Natural Science Foundation of China
Shenzhen Science and Technology Project
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10529283/10529298/10529370.pdf?arnumber=10529370
Reference21 articles.
1. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
2. Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
3. Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Reduced Vertical Nanowires Separation, New Work Function Metal Gate Solutions, and DC/AC Performance Optimization
4. Localized thermal effects in Gate-all-around devices
5. Analysis of Self-Heating Effects in Multi-Nanosheet FET Considering Bottom Isolation and Package Options
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1. A Neural Network-based Framework for Accelerated Device-Circuit Electrothermal Co-Simulations in GAAFETs;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10
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