Temperature Dependent Mismatch and Variability in a Cryo-CMOS Array with 30k Transistors
Author:
Affiliation:
1. Imec,Leuven,Belgium,3001
2. TU Wien,Institute for Microelectronics,Vienna,Austria,1040
3. Christian Doppler Laboratory for Single-Defect Spectroscopy in Semiconductor Devices
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9764406/9764408/09764594.pdf?arnumber=9764594
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1. Cooling the Chaos: Mitigating the Effect of Threshold Voltage Variation in Cryogenic CMOS Memories;Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design;2024-08-05
2. A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS;IEEE Journal of Solid-State Circuits;2024-07
3. Overview of Cryo-CMOS Devices and Circuits for Quantum Computing Applications;2023 IEEE International Symposium on Smart Electronic Systems (iSES);2023-12-18
4. The Future is Frozen: Cryogenic CMOS for High-Performance Computing (Invited);Chip;2023-12
5. Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs;IEEE Open Journal of Circuits and Systems;2023
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