System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents-Reference-Cited by-同舟云学术

System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents

Published:2022-03 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Reliability Physics Symposium (IRPS)
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Author:

Zahedmanesh Houman¹,Ciofi Ivan¹,Zografos Odysseas¹,Croes Kristof¹,Badaroglu Mustafa²

Affiliation:

1. imec,Leuven,Belgium

2. Qualcomm,Brussels,Belgium

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9764406/9764408/09764511.pdf?arnumber=9764511

Reference20 articles.

1. Electromigration Effects in Power Grids Characterized Using an On-Chip Test Structure with Poly Heaters and Voltage Tapping Points

2. Characterizing Electromigration Effects in a 16nm FinFET Process Using a Circuit Based Test Vehicle

3. Electromigration Effects in Power Grids Characterized From a 65 nm Test Chip

4. Microstructure based statistical model of electromigration damage in confined line metallizations in the presence of thermally induced stresses

5. Effect of reservoir on electromigration of short interconnects

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