Bias Temperature Instability on SiC n- and p-MOSFETs for High Temperature CMOS Applications-Reference-Cited by-同舟云学术

Bias Temperature Instability on SiC n- and p-MOSFETs for High Temperature CMOS Applications

Published:2022-03 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Reliability Physics Symposium (IRPS)
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Author:

Ashik Emran K¹,Isukapati Sundar B²,Zhang Hua³,Liu Tianshi³,Gupta Utsav³,Morgan Adam J²,Misra Veena¹,Sung Woongje²,Fayed Ayman³,Agarwal Anant K.³,Lee Bongmook¹

Affiliation:

1. North Carolina State University,Department of Electrical and Computer Engineering,Raleigh,NC,USA

2. State University of New York Polytechnic Institute,College of Nanoscale Science & Engineering,Albany,NY,USA

3. Ohio State University,Department of Electrical and Computer Engineering,Columbus,OH,USA

Funder

Advanced Research Projects Agency

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9764406/9764408/09764565.pdf?arnumber=9764565

Reference39 articles.

1. Two independent components modeling for Negative Bias Temperature Instability

2. Investigation and Modeling of Interface and Bulk Trap Generation During Negative Bias Temperature Instability of p-MOSFETs

3. Determination of hole effective mass in SiO2 and SiC conduction band offset using Fowler–Nordheim tunneling characteristics across metal-oxide-semiconductor structures after applying oxide field corrections

4. Density of interface states, electron traps, and hole traps as a function of the nitrogen density in SiO2 on SiC

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