High Mobility 4H-SiC P-MOSFET via Ultrathin ALD B₂O₃ Interlayer between SiC and SiO₂

Abstract

This article presents an innovative approach to achieve a high channel mobility for 4H-SiCp-MOSFET via dielectric-semiconductor interface engineering involving atomic layer deposition(ALD) of ultrathin B2O3 and SiO2 stacks. The application of ultrathin boron oxide via ALD introducesa highly manufacturable solution for the passivation of SiC interface. The interface states near valenceband reduces the channel mobility for SiC p-MOSFETs and increases the threshold voltage. Theintroduction of ultrathin B2O3 interlayer reduces the threshold voltage and improves the field effectmobility to 12.60 cm2/Vs while the p-MOSFET without the interlayer provides the mobility of 8.91cm2/Vs. This work also includes the optimization of the post-deposition annealing (PDA) conditionsspecific to ultrathin B2O3 and bulk SiO2 dielectric stack to obtain high field effect channel mobilityfor SiO2/SiC p-MOSFETs.