Numerical study on wafer level warpage evolution during chip to wafer hybrid bonding process-Reference-Cited by-同舟云学术

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Numerical study on wafer level warpage evolution during chip to wafer hybrid bonding process

Published:2021-12-07 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC)
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Author:

Ji Lin,Kawano Masaya,Tippabhotla Sasi Kumar,Loh Woon Leng

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9663571/9663865/09663908.pdf?arnumber=9663908

Reference5 articles.

1. Study on warpage and stress of TSV wafer with ultra-fine pitch vias for high density chip stacking

2. Modelling and characterization on wafer to wafer hybrid bonding technology for 3D IC packaging

3. Development of Wafer-Level Warpage and Stress Modeling Methodology and Its Application in Process Optimization for TSV Wafers

4. Die to Wafer Stacking with Low Temperature Hybrid Bonding

5. New chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Wafer Warpage Optimization Via Finite Element Analysis for a 3D Chiplet Package;2022 IEEE 24th Electronics Packaging Technology Conference (EPTC);2022-12-07

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