Author:
Wang Chua-Chin,Lu Shao-Wei
Cited by
3 articles.
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1. GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process;2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS);2024-04-22
2. A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process;2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2023-11-19
3. A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment;2021 IEEE Asia Pacific Conference on Circuit and Systems (APCCAS);2021-11-22