Author:
Vishnu Priya V,Priyarenjini A R,Kotha Naveen
Cited by
9 articles.
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1. A Technique to Optimize Clock Latency after CCOpt exploiting Useful Skew;2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2024-02-24
2. DEVELOPMENT OF PARAMETERIZED MODEL OF LOGIC ELEMENTS AT CLOCK TREE SYNTHESIS;Proceedings;2024
3. Timing ECO Approach Addressing Clock Gating Cells for Anti-Aging Purposes to Save Runtime;2023 International Conference on Electrical, Computer and Energy Technologies (ICECET);2023-11-16
4. A Configurable Multi Source Clock Tree Synthesis For High Frequency Network On Chips;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
5. Performance Analysis on Skew Optimized Clock Tree Synthesis;2022 Fourth International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT);2022-12-26