Exploring an On-Chip Sensor to Detect Unique Faults in RRAMs

Author:

Copetti T. S.1,Nilovic M.1,Fieback M.2,Gemmeke T.1,Hamdioui S.2,Bolzani Poehls L. M.1

Affiliation:

1. RWTH Aachen University,Germany

2. Delft University of Technology,The Netherlands

Funder

Federal Ministry of Education and Research

Publisher

IEEE

Reference27 articles.

1. Testing Open Defects in Memristor-Based Memories

2. Sneak-Path Testing of Crossbar-Based Nonvolatile Random Access Memories

3. Validating a DFT Strategy’s Detection Capability regarding Emerging Faults in RRAMs

4. Variability-Aware Modeling of Filamentary VCM based Bipolar Resistive Switching Cells Using SPICE Level Compact Models;bengel;IEEE Trans Circuits Syst,2020

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1. Lifecycle Management of Emerging Memories;2024 IEEE European Test Symposium (ETS);2024-05-20

2. Analyzing the Use of Temperature to Facilitate Fault Propagation in ReRAMs;2024 IEEE 25th Latin American Test Symposium (LATS);2024-04-09

3. A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing;Journal of Electronic Testing;2024-03-23

4. A Dynamic Testing Scheme for Resistive-Based Computation-In-Memory Architectures;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

5. Evaluating a New RRAM Manufacturing Test Strategy;2023 IEEE 24th Latin American Test Symposium (LATS);2023-03-21

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