Assessing device reliability margin in scaled CMOS technologies using ring oscillator circuits-Reference-Cited by-同舟云学术

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Assessing device reliability margin in scaled CMOS technologies using ring oscillator circuits

Published:2017-02 Issue: Volume: Page:
ISSN:
Container-title:2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM)
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Author:

Kerber A.,Cimino S.,Guarin F.,Nigam T.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7939937/7947483/07947495.pdf?arnumber=7947495

Cited by 20 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Ring Oscillator Aging Characterization in Conventional CMOS Technologies;2023 37th Symposium on Microelectronics Technology and Devices (SBMicro);2023-08-28

2. Investigation of CMOS reliability in 28 nm through BTI and HCI extraction;Microelectronics Reliability;2023-07

3. Analysis of HCD Effects for NMOS Transistor with Technology Scaling;SoutheastCon 2023;2023-04-01

4. Voltage Ramp Stress Test Optimization for Wafer Level Hot Carrier Monitoring in FinFET;2023 IEEE International Reliability Physics Symposium (IRPS);2023-03

5. CARAT – A reliability analysis framework for BTI-HCD aging in circuits;Solid-State Electronics;2023-03

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