A research of dual-port SRAM cell using 8T
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/5658734/5667273/05667886.pdf?arnumber=5667886
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Low Leakage SRAM Cell with Improved Stability for IoT Applications;Procedia Computer Science;2020
2. A 40nm Low Power High Stable SRAM Cell Using Separate Read Port and Sleep Transistor Methodology;2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS);2018-12
3. A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2018-11
4. A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology;Japanese Journal of Applied Physics;2018-03-22
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