Structured DFT Development Approach for Chisel-Based High Performance RISC-V Processors
Author:
Affiliation:
1. ShenZhen University,ShenZhen,China
2. Beijing Institute of open source chip,BeiJing,China
3. Chinese Academy of Sciences,Institute of Computing,BeiJing,China
4. PengCheng Laboratory,ShenZhen,China
Funder
Shenzhen Fundamental Research Program
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10301149/10301156/10301174.pdf?arnumber=10301174
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1. Minimal March Tests for Detection of Dynamic Faults in Random Access Memories
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3. Streaming scan network (SSN): An efficient packetized data network for testing of complex SoCs[C];côté;2020 IEEE International Test Conference (ITC),2020
4. The Challenges of Implementing an MBIST Interface: A Practical Application
5. Towards Developing High Performance RISC-V Processors Using Agile Methodology
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1. Advanced DFT Clock Control Architectures with Agile Development for Chisel-Based High Performance RISC-V Processors;2024 IEEE International Test Conference in Asia (ITC-Asia);2024-08-18
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