Author:
Kikuchi Shuya,Yotsuyanagi Hiroyuki,Hashizume Masaki
Cited by
5 articles.
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1. A High-Precision Delay Faults Testing Technique Based on the Improved DWR Structure;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20
2. Enabling In-Field Parametric Testing for RISC-V Cores;2023 IEEE International Test Conference (ITC);2023-10-07
3. Evaluation of a PUF Embedded in the Delay Testable Boundary Scan Circuit;2023 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC);2023-06-25
4. Testing Technologies for Analog/Mixed-Signal Circuits in IoT Era;IEEJ Transactions on Electronics, Information and Systems;2021-01-01
5. Current Research Topics on Boundary-Scan Technology;Journal of The Japan Institute of Electronics Packaging;2020-09-01