Dead Page and Dead Block Predictors: Cleaning TLBs and Caches Together

Author:

Mazumdar Chandrashis,Mitra Prachatos,Basu Arkaprava

Funder

VMware

Publisher

IEEE

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Direct Memory Translation for Virtualized Clouds;Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2;2024-04-27

2. Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

3. Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

4. IDYLL: Enhancing Page Translation in Multi-GPUs via Light Weight PTE Invalidations;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

5. DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore;IEEE Transactions on Parallel and Distributed Systems;2023-02-01

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