4 Bit and 8 Bit Convolution Using Vedic Multiplier-Reference-Cited by-同舟云学术

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4 Bit and 8 Bit Convolution Using Vedic Multiplier

Published:2022-11-18 Issue: Volume: Page:
ISSN:
Container-title:2022 International Conference on Emerging Trends in Engineering and Medical Sciences (ICETEMS)
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Author:

Kamdi Rahul¹,Thakre Prasheel²,Pathade Aniket³,Tiwari Sandeep Kumar⁴,Kalbande Kamlesh⁵

Affiliation:

1. Electronics & Telecommunication Engineering YCCE,Nagpur,India

2. Electronics & Communication Engineering RCOEM,Nagpur,India

3. Jawaharlal Nehru Medical College, DMIMS, Sawangi (M),Department of Directorate of Research,Wardha,India

4. Govt. Polytechnic,Electronics & Telecommunication Department,Yavatmal,India

5. Computer Science and Engineering (IoT) G H Raisoni College of Engineering,Nagpur,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10093235/10093239/10093621.pdf?arnumber=10093621

Reference12 articles.

1. High speed convolution and deconvolution algorithm (Based on Ancient Indian Vedic Mathematics)

2. Design of 8 Bit Vedic Multiplier Using Urdhva Tiryagbhyam Sutra With Modified Carry Save Adder

3. Design & implementation of fine ADC block in 8-b folding and interpolation

4. Design and Implementation of High-speed Low Voltage 4x4 Vedic Convolutor

5. Vedic Multiplier Implementation in VLSI

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Power-efficient VLSI realization of decimal convolution algorithms for resource-constrained environments: a design perspective in CMOS and double-gate CMOS technology;Microsystem Technologies;2024-04-21

2. Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model;Electronics;2024-03-29

3. Efficient Implementation of a 4x4 Enhanced Pipeline Multiplier Using Electric EDA Tool;2023 International Conference on Microelectronics (ICM);2023-12-17

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