Design of 8 Bit Vedic Multiplier Using Urdhva Tiryagbhyam Sutra With Modified Carry Save Adder
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8977147/9016382/09016965.pdf?arnumber=9016965
Cited by 17 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
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4. ASIC Design and Implementation of a Power-Delay Product Optimized Arithmetic Operational Unit;2023 International Conference on Modeling, Simulation & Intelligent Computing (MoSICom);2023-12-07
5. An Efficient High Performance GDI based 4-bit Vedic Multiplier in 32nm Technology;2023 Global Conference on Information Technologies and Communications (GCITC);2023-12-01
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