A novel energy efficient 4-bit vedic multiplier using modified GDI approach at 32 nm technology-Reference-Cited by-同舟云学术

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A novel energy efficient 4-bit vedic multiplier using modified GDI approach at 32 nm technology

Published:2024-05 Issue:10 Volume:10 Page:e31120
ISSN:2405-8440
Container-title:Heliyon
language:en
Short-container-title:Heliyon

Author:

Nishanth Rao K.,Sudha D.,Ibrahim Khalaf Osamah^ORCID,Abdulsaheb Ghaida Muttasher,Kumar Aruru Sai^ORCID,Priyanka S. Siva,Ouahada Khmaies,Hamam Habib

Funder

University of Johannesburg

Publisher

Elsevier BV

Reference33 articles.

1. Design of high-speed vedic multiplier using vedic mathematics techniques;Ganesh Kumar;Int. J. Sci. Technol. Res. Publ.,2012

2. Area efficient modified vedic multiplier;Challa Ram,2016

3. Design of 8-bit dadda multiplier using gate level approximate 4:2 compressor;Naresh,2022

4. Design of 8 bit vedic multiplier using urdhva tiryagbhyam sutra with modified carry save adder;Chandrashekara,2019

5. Analysis of 8-bit vedic multiplier using high speed CLA adder;Harshavardhan,2020

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