Vedic Multiplier Implementation in VLSI-Reference-Cited by-同舟云学术

Vedic Multiplier Implementation in VLSI

Published:2020 Issue: Volume:24 Page:2219-2230
ISSN:2214-7853
Container-title:Materials Today: Proceedings
language:en
Short-container-title:Materials Today: Proceedings

Author:

Kivi Sona M.,Somasundaram V.

Publisher

Elsevier BV

Subject

General Medicine

Reference25 articles.

1. Vedic Mathematics for VLSI Design;Anuradha Singh and Neetu Gupta;International Journal of Engineering Sciences and Research Technology (IJESRT) ISSN,2017

2. Low Power ALU Design by Ancient Mathematics;Anvesh Kumar and Ashish Raman;IEEE Transaction Computer,2010

3. Arun K. Patro and Kunal N. Dekate (2012) ‘A Transistor Level Analysis for a 8-bit Vedic Multiplier’, International Journal of Electronics Signals and Systems (IJESS) ISSN: 2231- 5969, Vol. 2, pp. 89-94.

4. High Speed Reconfigurable FFT Design by Vedic Mathematics;Raman;Journal of Computer Science and Engineering,2010

5. Low-Cost Fast VLSI Algorithm for Discrete Fourier Transform;Cheng;IEEE transaction on circuits and systems,2007

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