Balancing Testability and Security by Configurable Partial Scan Design-Reference-Cited by-同舟云学术

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Balancing Testability and Security by Configurable Partial Scan Design

Published:2018-08 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE International Test Conference in Asia (ITC-Asia)
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Author:

Chen Xi,Aramoon Omid,Qu Gang,Cui Aijiao

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8458101/8462928/08462963.pdf?arnumber=8462963

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of a Scan Chain for Side Channel Attacks on AES Cryptosystem for Improved Security;DEFENCE SCI J;2023

2. A Survey of Chips Security Technology Based on Scan Chain;2023 International Symposium of Electronics Design Automation (ISEDA);2023-05-08

3. A Low-overhead PUF-based Secure Scan Design;2023 24th International Symposium on Quality Electronic Design (ISQED);2023-04-05

4. Building Hardware Security Primitives Using Scan-based Design-for-Testability;2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS);2022-08-07

5. A Secure Scan Design based on Scan Scrambling by Pseudorandom Values and Circuit Itself;JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE;2021-12-31

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