Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels

Author:

Tsai Fong-Jyun,Ye Chong-Siao,Huang Yu,Lee Kuen-Jong,Cheng Wu-Tung,Reddy Sudhakar M.,Kassab Mark,Rajski Janusz,Zheng Shi-Xuan

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Revisiting Test Compression Configuration in Context of Multi-Core Testing Using Packetized Scan Network;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

2. A Novel Test Pattern Optimization Method Using Recurrent Neural Network;Journal of Circuits, Systems and Computers;2023-09-22

3. VTS 2022 Steering and Program Committees;2022 IEEE 40th VLSI Test Symposium (VTS);2022-04-25

4. Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations;2022 IEEE 40th VLSI Test Symposium (VTS);2022-04-25

5. An optimized DFT technology based on machine learning;2021 IEEE International Test Conference in Asia (ITC-Asia);2021-08-18

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