Impact of 1μ m TSV via-last integration on electrical performance of advanced FinFET devices-Reference-Cited by-同舟云学术

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Impact of 1μ m TSV via-last integration on electrical performance of advanced FinFET devices

Published:2018-03 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM)
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Author:

Hiblot Gaspard,Van Huylenbroeck Stefaan,Van der Plas Geert,De Wachter Bart,Chasin Adrian Vaisman,Kaczer Ben,Chiarella Thomas,Mitard Jerome,De Muynck Steven,Beyer Gerald,Beyne Eric

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8408585/8421409/08421473.pdf?arnumber=8421473

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Impact of Sub-μm Wafer Thinning on Latch-Up Risk in DTCO/STCO Scaling Era;IEEE Transactions on Electron Devices;2024-04

2. Low-Frequency Noise and Border Traps in Irradiated nMOS and pMOS Bulk Si FinFETs With SiO₂/HfO₂ Gate Dielectrics;IEEE Transactions on Nuclear Science;2023-04

3. A Comprehensive Review on FinFET in Terms of its Device Structure and Performance Matrices;Silicon;2022-05-14

4. The design and optimization of novel elliptic cylindrical through‐silicon via and its temperature characterization;Engineering Reports;2022-02-23

5. Antenna effect in 65nm NMOS devices with 9.5nm thick HfOx gate dielectric;2021 IEEE International Integrated Reliability Workshop (IIRW);2021-10-04

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