Impact of Sub-<i>μ</i>m Wafer Thinning on Latch-Up Risk in DTCO/STCO Scaling Era-Reference-Cited by-同舟云学术

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Impact of Sub-μm Wafer Thinning on Latch-Up Risk in DTCO/STCO Scaling Era

Published:2024-04 Issue:4 Volume:71 Page:2278-2283
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Serbulova Kateryna¹^ORCID,Chen Shih-Hung²^ORCID,Hellings Geert²^ORCID,Veloso Anabela²^ORCID,Jourdain Anne²^ORCID,Boeck Jo De¹,Groeseneken Guido¹^ORCID

Affiliation:

1. ESAT Department, Katholieke Universiteit Leuven, Leuven, Belgium

2. IMEC, Leuven, Belgium

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/16/10482422/10452317.pdf?arnumber=10452317

Reference16 articles.

1. The 3-D Interconnect Technology Landscape

2. Extreme Wafer Thinning and nano-TSV processing for 3D Heterogeneous Integration

3. Impact of 1μ m TSV via-last integration on electrical performance of advanced FinFET devices

4. Impact of wafer thinning on front-end reliability for 3D integration

5. Latchup test structure optimization in advanced CMOS technologies;Reiman

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