Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications-Reference-Cited by-同舟云学术

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Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications

Published:2023-05-21 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Gupta Mohit Kumar¹,Perumkunnil Manu¹,Biswas Dwaipayan¹,Chamazcoti Saeideh Alinezhad¹,Kar Gouri Sankar¹,Furnémont Arnaud¹,Ryckaert Julien¹

Affiliation:

1. imec,Leuven,Belgium

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181335.pdf?arnumber=10181335

Reference15 articles.

1. Architecting phase change memory as a scalable dram alternative

2. Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories

3. System exploration and technology demonstration of 3D Wafer-to-Wafer integrated STT-MRAM based caches for advanced Mobile SoCs

4. High-density SOT-MRAM technology and design specifications for the embedded domain at 5nm node

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