Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories-Reference-Cited by-同舟云学术

Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories

Published:2023-02 Issue:2 Volume:70 Page:733-746
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Alinezhad Chamazcoti Saeideh¹^ORCID,Gupta Mohit¹,Oh Hyungrock¹,Evenblij Timon¹^ORCID,Catthoor Francky¹^ORCID,Komalan Manu Perumkunnil¹^ORCID,Kar Gouri Sankar¹,Furnemont Arnaud¹

Affiliation:

1. IMEC, Leuven, Belgium

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/10027800/09964457.pdf?arnumber=9964457

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4. A memory controller with row buffer locality awareness for hybrid memory systems;yoon;arXiv 1804 11040,2018

5. Pin

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