System exploration and technology demonstration of 3D Wafer-to-Wafer integrated STT-MRAM based caches for advanced Mobile SoCs-Reference-Cited by-同舟云学术

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System exploration and technology demonstration of 3D Wafer-to-Wafer integrated STT-MRAM based caches for advanced Mobile SoCs

Published:2020-12-12 Issue: Volume: Page:
ISSN:
Container-title:2020 IEEE International Electron Devices Meeting (IEDM)
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Author:

Perumkunnil M.¹,Yasin F.¹,Rao S.¹,Salahuddin S. M.¹,Milojevic D.¹,Van der Plas G.¹,Ryckaert J.¹,Beyne Eric¹,Furnemont A.¹,Kar G.S.¹

Affiliation:

1. imec,Leuven,Belgium

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9371868/9371888/09372046.pdf?arnumber=9372046

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Lowering Latency of Embedded Memory by Exploiting In-Cell Victim Cache Hierarchy Based on Emerging Multi-Level Memory Devices;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

2. Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21

3. Technology Prospects for Data-Intensive Computing;Proceedings of the IEEE;2023-01

4. Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications;ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference (ESSDERC);2022-09-19

5. A Thermal Resistance Network Model of 3D-Stacked Stand-Alone MRAM;2022 Joint MMM-Intermag Conference (INTERMAG);2022-01

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