A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration
Author:
Affiliation:
1. Academy for Engineering and Technology, Fudan University,State Key Laboratory of Integrated Chips and System
Funder
National Key Research and Development Program of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181990.pdf?arnumber=10181990
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1. COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning
2. Interconnect in the Era of 3DIC
3. A Low-Cost and High-Throughput NoC-Aware Chip-to-Chip Interconnection
4. 184QPS/W 64Mb/mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System
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1. FPIA: Communication-Aware Multi-Chiplet Integration With Field-Programmable Interconnect Fabric on Reusable Silicon Interposer;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-09
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