A physical-based analytical model for hot-carrier induced saturation current degradation of p-MOSFET's
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx1/16/6559/00259624.pdf?arnumber=259624
Cited by 24 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Analysis of Abnormal GIDL Current Degradation Under Hot Carrier Stress in DSOI-MOSFETs;IEEE Transactions on Electron Devices;2022-11
2. On the Reliability Estimation of Analog CMOS Circuits Based on Statistical Methods;2019 11th International Conference on Electrical and Electronics Engineering (ELECO);2019-11
3. Insight Into Ballisticity of Room-Temperature Carrier Transport in Carbon Nanotube Field-Effect Transistors;IEEE Transactions on Electron Devices;2019-08
4. On-current Modeling of 70-nm PMOSFETs Dependent on Hot-carrier Stress Bias Conditions;JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE;2018-04-30
5. Drain-current Modeling of Sub-70-nm PMOSFETs Dependent on Hot-carrier Stress Bias Conditions;JSTS:Journal of Semiconductor Technology and Science;2017-02-28
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